The subject matter of the instant Patent Application is related to that disclosed in a pending U.S. Patent Application entitled MEMORY TESTER HAS MEMORY SETS CONFIGURABLE FOR USE AS ERROR CATCH RAM, TAG RAM""s, BUFFER MEMORIES AND STIMULUS LOG RAM, Ser. No. 09/672,650 and filed on Sep. 28, 2000. That disclosure describes aspects of operations called Address Classification and Data Classification that are of interest herein. For that reason U.S. patent application Ser. No. 09/672,650 is hereby expressly incorporated herein by reference.
The subject matter of the instant Patent Application is also related to that disclosed in a pending U.S. Patent Application entitled METHOD AND APPARATUS FOR NO-LATENCY CONDITIONAL BRANCHING, Ser. No. 09/659,256 and filed on Aug. 28, 2000. That disclosure is related to branching in a memory test program that is conditioned upon events within one Device Under Test. The instant Application extends that to a selected Device Under Test from among many such being tested. For that reason U.S. patent application Ser. No. 09/659,256 is hereby expressly incorporated herein by reference.
Electronics devices and capabilities have grown extremely common in daily life. Along with personal computers in the home, many individuals carry more than one productivity tool for various and sundry purposes. Most personal productivity electronic devices include some form of non-volatile memory. Cell phones utilize non-volatile memory in order to store and retain user programmed phone numbers and configurations when the power is turned off. PCMCIA cards utilize non-volatile memory to store and retain information even when the card is removed from its slot in the computer. Many other common electronic devices also benefit from the long-term storage capability of non-volatile memory in un-powered assemblies.
Non-volatile memory manufacturers that sell to the electronic equipment manufacturers require testers to exercise and verify the proper operation of the memories that they produce. Due to the volume of non-volatile memories that are manufactured and sold at consistently low prices, it is very important to minimize the time it takes to test a single part. Purchasers of non-volatile memories require memory manufacturers to provide high shipment yields because of the cost savings associated with the practice of incorporating the memory devices into more expensive assemblies with minimal or no testing. Accordingly, the memory testing process must be sufficiently efficient to identify a large percentage of non-conforming parts and preferably all non-conforming parts in a single test process.
As non-volatile memories become larger, denser and more complex, the testers must be able to handle the increased size and complexity without significantly increasing the time it takes to test them. Memory tester frequently run continuously, and test time is considered a major factor in the cost of the final part. As memories evolve and improve, the tester must be able to easily accommodate the changes made to the device. Another issue specific to testing non-volatile memories is that repeated writes to cells of the memories can degrade the overall lifetime performance of the part. Non-volatile memory manufacturers have responded to many of the testing issues by building special test modes into the memory devices. These test modes are not used at all by the purchaser of the memory, but may be accessed by the manufacturer to test all or significant portions of the memories in as little time as possible and as efficiently as possible. Some non-volatile memories are also capable of being repaired during the test process. The tester, therefore, should be able to identify: a need for repair; a location of the repair; the type of repair needed; and, must then be able to perform the appropriate repair. Such a repair process requires a tester that is able to detect and isolate a specific nonconforming portion of the memory. In order to take full advantage of the special test modes as well as the repair functions, it is beneficial for a tester to be able to execute a test program that supports conditional branching based upon an expected response from the device.
From a conceptual perspective, the process of testing memories is an algorithmic process. As an example, typical tests include sequentially incrementing or decrementing memory addresses while writing 0""s and 1""s into the memory cells. It is customary to refer to a collection of 1""s and 0""s being written or read during a memory cycle as a xe2x80x9cvectorxe2x80x9d, while the term xe2x80x9cpatternxe2x80x9d refers to a sequence of vectors. It is conventional for tests to include writing patterns into the memory space such as checkerboards, walking 1""s and butterfly patterns. A test developer can more easily and efficiently generate a program to create these patterns with the aid of algorithmic constructs. A test pattern that is algorithmically coherent is also easier to debug and use logical methods to isolate portions of the pattern that do not perform as expected. A test pattern that is generated algorithmically using instructions and commands that are repeated in programming loops consume less space intester memory. Accordingly, it is desirable to have algorithmic test pattern, generation capability in a memory tester.
Precise signal edge placement and detection is also a consideration in the effectiveness of a non-volatile memory tester. In order to identify parts that are generally conforming at a median while not conforming within the specified margins, a non-volatile memory tester must be able to precisely place each signal edge relative in time to another signal edge. It is also important to be able to precisely measure at which point in time a signal edge is received. Accordingly, a non-volatile memory tester should have sufficient flexibility and control of the timing and placement of stimuli and responses from the Device Under Test (memory).
Memory testers are said to generate transmit vectors that are applied (stimulus) to the DUT (Device Under Test), and receive vectors that are expected in return (response). The algorithmic logic that generates these vectors can generally do so without troubling itself about how a particular bit in a vector is to get to or from a particular signal pad in the DUT, as the memory tester contains mapping arrangements to route signals to and from the pins that contact the DUT. The collection of the algorithmic pattern generation, threshold setting, signal conditioning and comparison mechanisms, and the probes that connect that stuff to the DUT, is called a test site. In the simple case there is one DUT per test site.
Memory testers have interior test memory that is used to facilitate the test process. This interior test memory may be used for several purposes, among which are storing transmit vectors ahead of time, as opposed to generating them in real time, storing expected receive vectors, and storing a variety of error indications and other information concerning DUT behavior obtained during testing. (There are also housekeeping purposes internal to the operation of the memory tester that use RAM and that may appear to fall within the purview of the phrase xe2x80x9cinterior memory.xe2x80x9d These are private to the internal operation of the tester, tend to not be visible at the algorithmic level, and are comparable to executable instruction stores and to internal control registers. That memory is described as xe2x80x9cinterior control memory,xe2x80x9d and is excluded from what is meant herein by the term xe2x80x9cinterior test memory,xe2x80x9d which we use to describe memory used to store bit patterns directly related to the stimulus of, and response from, the DUT.) It is easy to appreciate that this interior test memory needs to operate at least as fast as the tests being performed; a very common paradigm is for the interior test memory (or some portion thereof) to be addressed by the same address (or some derivative thereof) as is applied to the DUT. What is then stored at that addressed location in interior test memory is something indicative of DUT behavior during a test operation performed on the DUT at that address. Algorithmic considerations within the test program may mean that the sequence of addresses associated with consecutive transmit vectors can be arbitrary. Thus, the interior memory needs to have the dual attributes of high speed and random addressability. SRAM comes to mind immediately as being fast, easy to control and tolerant of totally random addressing. Indeed, conventional memory testers have used SRAM as their interior test memory.
Unfortunately, SRAM is quite expensive, and this has limited the amount of interior test memory with which memory testers have had to work. The result is limits on memory tester functionality that are imposed by a shortage of memory. DRAM is significantly less expensive, but cannot tolerate random addressing and still perform at high speed.
DRAM can replace SRAM as the interior test memory in a memory tester. As briefly described below, the problem of increasing the speed of DRAM operation for use as interior test memory can be solved by increasing the amount of DRAM used, in place of increasing its speed. Numbers of identical Banks of DRAM are treated as Groups. A combination of interleaving signals for different Banks of memory in a Group thereof and multiplexing between those Groups of Banks slows the memory traffic for any one Bank down to a rate that can be handled by the Bank.
At the top level of interior test memory organization there are four Memory Sets, each having its own separate and independent address space and performing requested memory transactions. Two are of DRAM as described above, and two are of SRAM. Each Memory Set has its own controller to which memory transactions are directed. As to externally visible operational capabilities as memories, all four Memory Sets are essentially identical. They differ only in their size of memory space and how they are internally implemented: The SRAM Memory Sets do not employ multiplexing and interleaving, since they are fast enough to begin with. Despite their independence, Memory Sets of the same type (of SRAM or of DRAM) may be xe2x80x9cstacked,xe2x80x9d which is to say treated a one larger address space.
Thus it is that the interior test memory of the tester is divided into four Memory Sets, two of which are xe2x80x9cinternalxe2x80x9d SRAM""s and two of which are xe2x80x9cexternalxe2x80x9d DRAM""s. To be sure, all this memory is physically inside the memory tester; the terms xe2x80x9cinternalxe2x80x9d and xe2x80x9cexternalxe2x80x9d have more to do with a level of integration. The SRAM""s are integral parts of a VLSI (Very Large Scale Integration) circuit associated with the tester""s central functional circuitry, while the DRAM""s are individual packaged parts mounted adjacent the VLSI stuff. The amount of SRAM is fairly small, (say, around a megabit per Memory Set) while the amount of DRAM is substantial and selectable (say, in the range of 128 to 1024 megabits per Memory Set). The SRAM Memory Sets are always present, and may be used for any suitable purpose, such as storing the expected content of a DUT that is a ROM (Read Only Memory). The DRAM Memory Sets, although actually optional, are typically used for creating a trace for subsequent analysis leading to repair, although there are also other uses. The tester does not enforce major distinctions between the SRAM and DRAM Memory Sets, as to different purposes for which they may be used. There are some practical major distinctions that arise mostly as a matter of size. The SRAM Memory Sets are small, while the DRAM Memory Sets are potentially huge. The person or persons creating the test programming generally make the decisions concerning how the various Memory Sets are to be used. There are also a few minor distinctions where a particular operational feature of the memory tester requires the use of a specific Memory Set. These cases usually arise out of economic or performance considerations that require a dedicated hardware path to a Memory Set. It is expedient to simply pick a likely one, and let it go at that.
The advent of substantial amounts of interior test memory (in the form of the DRAM Memory Sets) raises the issue of how this additional amount of memory can be used to facilitate the operation of desirable features within the memory tester. In the tester of interest the interior test memory subsystem is extremely flexible, in that despite having a native word width of thirty-two bits, the effective word width can be any power of two (up to 25=32), with a corresponding increase in address space for narrower words. There is an extensive address mapping capability, both for addressing DUT""s and for addressing interior test memory, substantial data classification and address classification mechanisms that facilitate multiple Tag RAM""s and other error analysis tools, all of which are made more practical by having lots of interior test memory. Moreover, these enhancements made possible by more memory do not exist in a vacuum; they are very valuable in the testing of certain types of memory parts.
Despite that recent advances have produced memory parts of truly enormous capacity (512MB) and wide data paths (thirty-two bits), yesterday""s four, eight and sixteen bit parts are still solidly in commercial service. It is even the case that some high capacity parts have been xe2x80x9cthrottled downxe2x80x9d to a narrow path for address and data, even at the expense of serialization or of supporting multiple cycle segmentation to transport whole data of a wider native word width. There are various reasons for this situation: either small parts are all that is needed, or, the application is such that big parts can have narrow paths (video applications that are always addressed sequentially). Suffice it to say that there are good economic reasons why memory parts with narrow paths are well received in the market. And that means that they have to be tested.
Consider what this means to a purveyor of a top of the line memory tester that boasts of being able to test parts requiring up to sixty-four channels. From time to time his customer wants to check eight bit parts. What with supplies and ground, I/O bus, clocks and assorted control lines, there are perhaps from twelve to sixteen channels that will be needed. Suppose it is fourteen. Does this mean that fifty channels will be left unused when the part to be tested is located under the test head? Considering that the memory industry considers time on the tester as money, and that memory tester often run twenty-four hours a day, seven days a week, our purveyor and his customer are both interested in ways that make the memory tester more competitive. To the customer, unused test capacity is wasted money. What the designers of the memory tester can do is increase the flexibility and configurability of their machine to allow it to test more parts at once. This defuses the need for the customer to purchase many different models, and even though his per tester cost remains at the top of the line level, the customer gets a fair value in terms of increased throughput, longer life of the investment, etc.
The tester""s designers note that sixty-four channels is enough to do as many as sixteen channels four times, and readily reach the conclusion that a combination of four undiced DUT""s on a wafer, or four packaged parts, can be construed as some strange single big part that just happens to look exactly like the union of four little parts. There is no question about it: in theory, those four little parts can be tested at the same time, simultaneously, under the same test head. The trouble is that it is awkward and inconvenient. The test program has to be re-written, which is so disgusting that it is not considered a viable solution. This is especially so for flash memory parts, since a failure in one DUT can expose other DUT""s being tested under the same test head to undesirable, or even harmful, stresses having to do with excessive numbers of write cycles or repeated high drive levels, brought about by programmed-in escalation triggered by marginal or failed behavior of one DUT. But the designers of test programs want to avoid punishing the innocent along with the guilty, so to speak. (The class of so-called xe2x80x9cNANDxe2x80x9d parts is especially sensitive to this sort of thing.) The writing of a single-thread-of-control test program that emulates a four-threads-of-control test program, where each of those four threads (what is done for an individual DUT) has conditional branching and other result dependent behavior is, well, a nightmare. That sort of situation would seem to need four independent execution mechanisms with four simple programs whose internal execution paths could independently diverge as needed. But then, how to return to the other extreme, where all sixty-four channels need to be controlled by one program testing an actual single big part? Four little processors do not make a big processor!
There has to be a better way than putting four big processors, or three little ones and one big one, behind the test head. Especially so if test sites are also to be capable of being bonded together to increase their size.
Some types of memory devices require that a write to a location be done many times in order to xe2x80x9cprogramxe2x80x9d that location with the written value. There is also an issue called xe2x80x9coverprogrammingxe2x80x9d that refers to needlessly continuing to write the value to be programed at a location after it has been successfully programmed. Such continued writing (overprogramming) can damage the part. There are various techniques that have been used to prevent overprogramming. Since these programming activities usually take place within tightly written loops embedded in other functions, any extraneous activity in the interior loops is inefficient. It would therefore be desirable if the test program overhead needed to program a location and prevent overprogramming could be significantly reduced.
Thus, the situation is this. We have a powerful tester that has an abundance of channels per test site, with powerful algorithmic capabilities to generate patterns and perform failure analysis, and that can attempt repairs by blowing fusible elements in the DUT to cause substitute circuits to replace bad ones. The tester has lots of memory that is easily partitioned, reconfigured and variously mapped, and as such lends itself to maintaining nicely separated results for multiple DUT""s, if we could just test them all at the same time on the same test site. But the size of the algorithmic control mechanism of the test site is determined by the maximum number of channels, and does not readily decompose into usable smaller mechanisms. And yet there are all these small parts out there to be tested, and time on the tester is money.
What to do?
The internal architecture of a memory tester is enhanced to support the testing of multiple DUT""s of the same type at a test site, while requiring only minor modifications to a test program that would ordinarily be used to test a single DUT. The multiple DUT""s are electrically isolated from one another, but are, at least at the outset, given the same stimulus from which the same response is expected. To do this the DUT""s are each associated with collections of channels that are to be used to test their respective DUT""s. The tester can be instructed to replicate the segments of the test vectors needed to test one DUT on the channels for the other DUT""s. This produces patterns of (sequences of) transmit (stimulus) and receive (response) vectors that are xe2x80x9cn-many DUT""s wide,xe2x80x9d as it were. Conditional branching within the test program in response to conditions in the receive vectors (DUT failure) is supported by recognizing several types of error indications and an ability to selectively disable the testing of one or more DUT""s while continuing to test the one or more that are not disabled. The error indications include per channel functional error flags and per DUT functional error flags, as well as per DUT parametric error flags. The per DUT functional error flags are created from an OR""ing of the per channel functional error flags done in accordance with the DUT to channel association. These flags are reported back to the test program, which can then take various appropriate actions that alter program flow to invoke special testing or other actions for the suspect DUT. The error conditions are also detected by pre-programmed mechanisms within the circuitry that applies transmit vectors and evaluates receive vectors. These latter pre-programmed mechanisms produce actions that include, on a per channel basis, the ability to alter the drive and receive formats for the DUT signal of that channel, and the ability to alter a data value associated with the DUT signal of that channel. Also included are ways to remove or limit stimulus to particular DUT""s, as well as ways to make all comparisons for a particular DUT appear to be xe2x80x9cgood,xe2x80x9d regardless of the true facts. These latter mechanisms remove the need for multiple threads of execution in the test program.
The test program is thus empowered to simultaneously test a plurality (up to four in a preferred embodiment) of DUT""s xe2x80x9cin parallelxe2x80x9d as long as no errors are reported. Upon an error the test program can branch to an error investigation routine that exercises only the suspect DUT by temporarily disabling the good DUT""s while continuing to exercise the bad DUT. If the bad DUT is defective beyond repair, or is unsafe to leave powered up, it can be disabled, the other DUT""s re-enabled and regular testing resumed. In this way, a single thread of execution (that would exist in essentially this same form for testing a single DUT) can be selectively switched between (executed on behalf of) the different DUT""s on an as needed basis, driven by which one(s) fail(s). During these selectively switched intervals simultaneous testing of all DUT""s is suspended in favor of a digression that tests a particular DUT of interest. To be sure, this switching and jumping to execute digressions is also programmatically defined to occur in response to contingent events discovered while testing. Part of this programmatic definition is easily performed modifications to the single threaded test program (which remains single threaded) and part of it is pre-configuration of various hardware assist mechanisms.
These features may be combined with automatic reading of a special bad block table created in interior test memory to facilitate the testing of memory parts that have an internal block structure, by automatically disabling, and removing from further influence on the test program, actions related to a bad block. That bad block may or may not be in a DUT that is being tested in a multi-DUT fashion. These features may also be used to prevent overprogramming.